This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-271251, filed Sep. 24, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a digital PLL (phase locked loop) circuit, and more particularly to a PLL circuit which uses a variable-frequency ring oscillator as a VCO (voltage controlled oscillator), the variable-frequency ring oscillator including a delay circuit including delay elements connected in a multi-stage and constructed so that the delay elements can be selected in number, and a variable capacitor connected to the delay circuit.
A conventional digital PLL circuit has used a variable-frequency ring oscillator. The variable-frequency ring oscillator is assembled by a multistage delay circuit, a multiplexer for determining the number of delay stages of the delay circuit, an inverter circuit for inverting the output signal of the multiplexer, an offset delay circuit for delaying the output signal of the inverter circuit for the length of input offset delay time and feeding back the delayed signal to the first stage of the delay circuit, and a variable capacitor connected to the first stage of the delay circuit and the ground. Two stages of inverters are connected to the output of the multiplexer. The output signal of the inverter at the latter stage is the output of the ring oscillator. There is further provided a delay/capacitance controller that generates a control signal for controlling the value capacitance of the variable capacitor (the number of capacitors connected in parallel) and the selection of the input to the multiplexer (the selection of the number of delay stages of the delay circuit).
In the delay-element-selection-type digital PLL circuit using the ring oscillator including two stages of inverters as a VCO, the output of the ring oscillator is frequency-divided by a frequency divider. A phase comparator compares the divided output with a phase reference signal, generates a control signal corresponding to the comparison output, and inputs the control signal to the delay/capacitance controller.
With the digital PLL circuit constructed as described above, the frequency of oscillation of the ring oscillator is roughly adjusted by the number of delay stages of the delay circuit and then finely adjusted by the value of capacitance of the variable capacitor (or the number of capacitors connected in parallel), thereby producing the desired output frequency.
Now, consider a case where the number of delay stages of the delay circuit and/or the number of unit capacitors connected in parallel are changed by the PLL operation according to the change of the frequency control input from the state where the ring oscillator is oscillating at the frequency determined by a specific number of delay stages of the delay circuit and/or a specific number of unit capacitors connected in parallel.
At this time, if only the number of unit capacitors connected were changed, the output frequency of the PLL circuit would result in only a change in the value of capacitance of the variable capacitor. Since only the change of the number of unit capacitors connected in parallel cannot produce the desired change of the frequency of oscillation, if the number of delay stages of the delay circuit were also changed, the PLL output frequency would change greatly due to variations in the delay characteristics of the delay circuit, causing jitters (fluctuations in the edge of the output signal) in the output frequency.
The change of the delay characteristic due to variations in the manufacture can be considered to be the cause of the occurrence of jitters in the output frequency. Namely, when variations in the manufacture result in variations in the amount of delay in one stage of the delay circuit or the amount of delay in a single unit capacitor, the following can be considered. The length of delay time in minimizing the value of capacitance of the variable capacitor when the number of delay stages of the delay circuit is increased by one is larger than the length of delay time in maximizing the value of capacitance of the variable capacitor. Moreover, when the number of delay stages of the delay circuit is changed, with the value of capacitance of the variable capacitor remaining unchanged, a variation in the length of delay time is too great, permitting jitters to occur in the PLL output frequency, which contributes to the deterioration of the PLL characteristic.
To avoid such a problem, an attempt is made to secure the continuity of the change of the length of delay time. For example, the delay circuit and variable capacitor are designed in advance to cause a certain number of delay stages of the delay circuit and its adjacent number of delay stages to have an overlap area where the length of delay time at one end of the delay time characteristic of the former overlaps with that at one end of the delay time characteristic of the latter. When the number of delay stages of the delay circuit is changed to the adjacent number of delay stages, the value of capacitance of the variable capacitor is changed to the value (other than the minimum and maximum values of capacitance) at which the length of delay time corresponding to the overlap area is obtained.
Such measures, however, cannot avoid variations in the delay characteristic due to variations in the manufacture. In a case where the amount of delay in one stage of the delay circuit or the amount of delay in a single unit capacitance varies, when the number of delay stages of the delay circuit has been changed, a variation in the length of delay time is too great, permitting jitters to occur, which contributes to the deterioration of the PLL characteristic.
As described above, a variable-frequency ring oscillator used as a VCO in a conventional digital PLL circuit has the following problem: when the number of delay stages of the delay circuit is changed and therefore the frequency is in transition, jitters occur in the PLL output frequency due to variations in the delay characteristic resulting from variations in the manufacture, which contributes to the deterioration of the PLL characteristic.
The object of the present invention is to provide a digital PLL circuit capable of not only making desired corrections in the transition of frequency, even when there are variations in the delay characteristic due to variations in the manufacture of variable-frequency ring oscillators but also preventing the occurrence of jitters in the PLL output frequency and the deterioration of the PLL characteristic.
According to the present invention, there is provided a digital PLL circuit comprising a variable-frequency ring oscillator, a frequency divider for frequency-dividing the output signal of the ring oscillator, a phase comparator for comparing the frequency-divided output of the frequency divider with a phase reference signal, and a control signal generator for generating a control signal corresponding to the comparison output of the phase comparator and supplying the control signal to the ring oscillator, wherein the ring oscillator includes delay circuits connected in a multistage manner, a multiplexer for selecting one of the output signals of the delay circuits connected in a multistage manner and determining the number of stages of delay circuits, an inverting delay circuit for inverting the output signal of the multiplexer, a variable capacitor so constructed that the value of its capacitance is changed by switching the number of unit capacitors connected in parallel, and a delay/capacitance controller for referring to correction information and controlling the selection of delay circuits by the multiplexer and the switching of the variable capacitor.